SLG46621

Dual Supply, 17-GPIO, 6 ACMPs, 3 DCMPs/PWMs, 2 DACs, 26 LUTs (max.), 10 CNT/DLY (max.), 12 DFF/LATCH (max.) and other Macrocells

SLG46621提供小,低功率组件for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro cells of the SLG46621. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The additional power supply (VDD2) on the SLG46621 provides the ability to interface two independent voltage domains within the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically by internal logic) to both VDD and VDD2 voltage domains. Using the available macro-cells designers can implement mixed-signal functions bridging both domains or simply pass through level-translation in both High to Low and Low to High directions.

8-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC);

ADC 3-bit Programmable Gain Amplifier (PGA);

Two Digital-to-Analog Converters (DAC);

Six Analog Comparators (ACMP);

Two Voltage References (Vref);

Twenty Five Combinatorial Look Up Tables (LUTs):

• Eight 2-bit LUTs;
• Sixteen 3-bit LUTs;
• One 4-bit LUT;

One Combination Function Marcocells:

• Pattern Generator or 4-bit LUT;

Three Digital Comparators/Pulse Width Modulators (DCMPs /PWMs) w/Selectable Deadband;

Ten Counters/Delays (CNT/DLY):

• Two 14-bit Delay/Counter;
• One 14-bit Delay/Counter (Wake-Sleep Control);
• One 14-bit Delay/Counter/Finite State Machine;
• Five 8-bit Delay/Counter;
• One 8-bit Delay/Counter/Finite State Machine;

Twelve D Flip-flops/Latches;

Two Pipe Delays - 16 stage/2 output;

Two Bandgaps;

Two Programmable Delays w/ Edge Detection;

Three Internal Oscillators:

• Low-Frequency;
• Ring;
• RC 25 kHz and 2 MHz;

Power-On-Reset (POR);

Slave SPI.

Logic & Mixed Signal Circuits

Highly Versatile Macrocells

Read Back Protection (Read Lock)

1.8 V (±5%) to 5 V (±10%) VDD

1.8 V (±5%) to 5 V (±10%) VDD2 (VDD2 ≤ VDD)

Operating Temperature Range: -40°C to 85°C

RoHS Compliant / Halogen-Free

Personal Computers and Servers

PC Peripherals

Consumer Electronics

Data Communications Equipment

Handheld and Portable Electronics

SLG46621V: STQFN-20 (2.0 x 3.0 x 0.55 mm, 0.4 mm pitch)

The product ID suffix indicates the package style.