1 month ago
about boot option and reset
Posted byyykx75 points 5 replies1. booting option, we know it can boot from otp, iic, uart..., if I want to make it boot from uart (for example the code is transmit from other MCU with UART), what's the protocol?
2. after watchdog reset, will it run from "The boot ROM code" (reads the Application Programmed flags from the OTP header to identify
whether the chip is in Development mode or Normal mode.), or just run from the Ram code?
thanks.
1 month ago
1. it no mean "UM-B-143 Dialog External Processor Interface".
in "an-b-072-da14531_booting_options_v1.4" page 26,ootRom sequence, How the chip to select uart, spi, iic?
what I need is that: for development mode, use an MCU instead of an EEPROM, to store code, after development, burn code to OTP.
when 14531 booting ,the MCU download the code to 14531 with uart or spi, just like an eeprom.
thanks again!
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1 month ago
Hi yykx,Hi
The DA14531 is booting from specific pins – please see Table 1( page 5) from the AN-B-072-DA14531_Booting_options:
//www.wsdof.com/sites/default/files/2021-01/AN-B-072-DA14531_Booting_options_v1.5.pdf
The booter will try to boot from the above serial interfaces in the order from Step 1 to step 6. For example, booting from 1 wire UART (step 2 ) is prior from booting from I2C (step 6).
According to the BootROM sequence (attached), for instance, if the DA14531 fails to boot from 1 wire UART on P05, then it will try to boot from the next step with is booting from 1 wire UART on P03.
Thanks, PM_Dialog
1 month ago
Hi Dialog
is there any protocol? or just need send code data with 115200 when in step 2.
thank you!
1 month ago
Hi There,
1. Could you please clarify this statement? Do you mean some this :UM-B-143 Dialog External Processor Interface?
2. If the WDOG generates HW reset then the BootROM will start executing again. Please check section 22.2 in the datasheet. According to the datasheet, if WATCHDOG_CTRL_REG[NMI_RST] = 0, the watchdog timer will generate an NMI when it reaches 0. If WATCHDOG_CTRL_REG[NMI_RST] = 1, the watchdog timer generates a WDOG reset when it becomes less than or equal to 0. The WDOG reset is one of the system (SYS) reset sources and resets almost the whole device, including resetting the WATCHDOG_REG register to 255. Refer to the POR, HW, and SW Reset
section for an overview of the complete reset circuit and conditions. So, in order to run the RAM after a WDOG reset, the WATCHDOG_CTRL_REG[NMI_RST] should be set to 1 and remap to RAM in NMI_HandlerC().
Thanks, PM_Dialog