自定义闪存驱动程序DA14695

嗨对话团队，

目前，我正在尝试根据DA14695培养我的定制板。当我在RAM模式（我的应用程序或来自SDK的任何应用程序中的应用程序时，一切都很好。但是当我试图将它加载到QSPI闪存时，我收到了这条消息

cli_programmer 1.26.
版权所有（c）2015-2019对话半导体雷竞技电竞平台

未指定引导加载程序文件，使用内部uartboot.bin

上传引导装载程序/应用程序可执行文件...
可执行文件已上载。

写地址：0x00002000偏移量：00000000块大小：0x00002000

之后，它卡住了。我创建了Flash驱动程序，如您的教程中所述，重建UartBoot和CLI_Programmer为我的主机配置（DA1469X-00_RELEASE_STORATIC_LINUX）可以验证附加的驱动程序和.xml吗？

/ ** * \ addtogroup PLA_BSP_SYSTEM * \ {* \ addtogroup PLA_MEMORY * * \ {* / / ** **************************************************************************************** * * @file qspi_adesto.h * * @brief QSPI flash driver for Adesto flashes - common code * **************************************************************************************** */ #ifndef _QSPI_ADESTO_H_ #define _QSPI_ADESTO_H_ #define ADESTO_ID 0x1F #include "qspi_common.h" #define AT25SL_WRITE_ENABLE 0x06 #define AT25SL_WRITE_ENABLE_FOR_VOLATILE 0x50 #define AT25SL_WRITE_DISABLE 0x04 #define AT25SL_READ_STATUS_REGISTER1 0x05 #define AT25SL_READ_STATUS_REGISTER2 0x35 #define AT25SL_WRITE_STATUS_REGISTER1 0x01 #define AT25SL_WRITE_STATUS_REGISTER2 0x31 #define AT25SL_READ_DATA 0x03 #define AT25SL_FAST_READ_DATA 0x0B #define AT25SL_PAGE_PROGRAM 0x02 #define AT25SL_ENABLE_QPI 0x38 #define AT25SL_BLOCK_ERASE_4KB 0x20 #define AT25SL_BLOCK_ERASE_32KB 0x52 #define AT25SL_BLOCK_ERASE_64KB 0xD8 #define AT25SL_CHIP_ERASE 0xC7 #define AT25SL_ERASE_PROGRAM_SUSPEND 0x75 #define AT25SL_ERASE_PROGRAM_RESUME 0x7A #define AT25SL_DEEP_POWER_DOWN 0xB9 #define AT25SL_RELEASE_DEEP_POWER_DOWN 0xAB #define AT25SL_READ_DEVICE_ID 0x90 #define AT25SL_READ_JEDEC_ID 0x9F #define AT25SL_RESET_ENABLE 0x66 #define AT25SL_RESET 0x99 #define AT25SL_ENTER_SECURED_OTP 0xB1 #define AT25SL_EXIT_SECURED_OTP 0xC1 #define AT25SL_READ_SECURITY_REG 0x2B #define AT25SL_WRITE_SECURITY_REG 0x2F #define AT25SL_READ_SFDP_REG 0x5A #define AT25SL_FAST_READ_DUAL_OUTPUT 0x3B #define AT25SL_FAST_READ_DUAL_IO 0xBB #define AT25SL_READ_DEVICE_ID_DUAL 0x92 #define AT25SL_FAST_READ_QUAD_OUTPUT 0x6B #define AT25SL_FAST_READ_QUAD_IO 0xEB #define AT25SL_QUAD_PAGE_PROGRAM 0x33 #define AT25SL_READ_QUAD_DEVICE_ID 0x94 #define AT25SL_WORD_READ_QUAD_IO 0xE7 #define AT25SL_SET_BURST_WITH_WRAP 0x77 #define AT25SL_WRITE_ENABLE_QPI 0x06 #define AT25SL_WRITE_ENABLE_FOR_VOLATILE_QPI 0x50 #define AT25SL_WRITE_DISABLE_QPI 0x04 #define AT25SL_READ_STATUS_REGISTER1_QPI 0x05 #define AT25SL_READ_STATUS_REGISTER2_QPI 0x35 #define AT25SL_WRITE_STATUS_REGISTER1_QPI 0x01 #define AT25SL_WRITE_STATUS_REGISTER2_QPI 0x31 #define AT25SL_FAST_READ_DATA_QPI 0x0B #define AT25SL_PAGE_PROGRAM_QPI 0x02 #define AT25SL_BLOCK_ERASE_4KB_QPI 0x20 #define AT25SL_BLOCK_ERASE_32KB_QPI 0x52 #define AT25SL_BLOCK_ERASE_64KB_QPI 0xD8 #define AT25SL_CHIP_ERASE_QPI 0xC7 #define AT25SL_ERASE_PROGRAM_SUSPEND_QPI 0x75 #define AT25SL_ERASE_PROGRAM_RESUME_QPI 0x7A #define AT25SL_DEEP_POWER_DOWN_QPI 0xB9 #define AT25SL_RELEASE_DEEP_POWER_DOWN_QPI 0xAB #define AT25SL_READ_DEVICE_ID_QPI 0x90 #define AT25SL_READ_JEDEC_ID_QPI 0x9F #define AT25SL_ENTER_SECURITY_QPI 0xB1 #define AT25SL_EXIT_SECURITY_QPI 0xC1 #define AT25SL_READ_SECURITY_REG_QPI 0x2B #define AT25SL_WRITE_SECURITY_REG_QPI 0x2F #define AT25SL_FAST_READ_QUAD_IO_QPI 0xEB #define AT25SL_RESET_ENABLE_QPI 0x66 #define AT25SL_RESET_QPI 0x99 #define AT25SL_DISABLE_QPI 0xFF #define AT25SL_BURST_READ_WITH_WRAP_QPI 0x0C #define AT25SL_SET_READ_PARAMETER_QPI 0xC0 #define AT25SL_QUAD_PAGE_PROGRAM_QPI 0x33 /* Suspend */ #define AT25SL_STATUS2_SUS_BIT 7 #define AT25SL_STATUS2_SUS_MASK (1 << AT25SL_STATUS2_SUS_BIT) /* QPI Enable */ #define AT25SL_STATUS2_QE_BIT 1 #define AT25SL_STATUS2_QE_MASK (1 << AT25SL_STATUS2_QE_BIT) // Flash power up/down timings #define AT25SL_POWER_DOWN_DELAY_US 3 #define AT25SL_RELEASE_POWER_DOWN_DELAY_US 3 #define AT25SL_POWER_UP_DELAY_US 10 #if (dg_configFLASH_POWER_OFF == 1) /** * \brief uCode for handling the QSPI FLASH activation from power off. */ /* * Not tested * * Delay 10usec * 0x01 // CMD_NBYTES = 0, CMD_TX_MD = 0 (Single), CMD_VALID = 1 * 0xA0 // CMD_WT_CNT_LS = 160 --> 10000 / 62.5 = 160 = 10usec * 0x00 // CMD_WT_CNT_MS = 0 * Exit from Fast Read mode * 0x09 // CMD_NBYTES = 1, CMD_TX_MD = 0 (Single), CMD_VALID = 1 * 0x00 // CMD_WT_CNT_LS = 0 * 0x00 // CMD_WT_CNT_MS = 0 * 0xFF // Enable Reset * (up to 16 words) */ const uint32_t at25sl_ucode_wakeup[] = { 0x09000001 | (((uint16_t)(AT25SL_POWER_UP_DELAY_US*1000/62.5) & 0xFFFF) << 8), 0x00FF0000, }; #elif (dg_configFLASH_POWER_DOWN == 1) /** * \brief uCode for handling the QSPI FLASH release from power-down. */ /* * Not tested * * 0x09 // CMD_NBYTES = 1, CMD_TX_MD = 0 (Single), CMD_VALID = 1 * 0x30 // CMD_WT_CNT_LS = 3000 / 62.5 = 48 // 3usec * 0x00 // CMD_WT_CNT_MS = 0 * 0xAB // Release Power Down * (up to 16 words) */ const uint32_t at25sl_ucode_wakeup[] = { 0xAB000009 | (((uint16_t)(AT25SL_RELEASE_POWER_DOWN_DELAY_US*1000/62.5) & 0xFFFF) << 8), }; #else /** * \brief uCode for handling the QSPI FLASH exit from the "Continuous Read Mode". */ /* * Not tested * * 0x25 // CMD_NBYTES = 4, CMD_TX_MD = 2 (Quad), CMD_VALID = 1 * 0x00 // CMD_WT_CNT_LS = 0 * 0x00 // CMD_WT_CNT_MS = 0 * 0x55 // Clocks 0-1 (A23-16) * 0x55 // Clocks 2-3 (A15-8) * 0x55 // Clocks 4-5 (A7-0) * 0x55 // Clocks 6-7 (M7-0) : M5-4 != '10' ==> Disable "Continuous Read Mode" * (up to 16 words) */ const uint32_t at25sl_ucode_wakeup[] = { 0x55000025, 0x00555555, }; #endif static bool flash_at25sl_is_suspended(HW_QSPIC_ID id); static void flash_at25sl_initialize(HW_QSPIC_ID id); /** * \brief Enable volatile writes to Status Register bits * \details When this command is issued, any writes to any of the Status Registers of the Flash are * done as volatile writes. This command is valid only when the Write Status Register command * follows. * * \param[in] id QSPI controller id * * \note This function blocks until the Flash has processed the command. */ __STATIC_FORCEINLINE __UNUSED void flash_at25sl_wre_volatile(HW_QSPIC_ID id) { uint8_t cmd[] = { AT25SL_WRITE_ENABLE_FOR_VOLATILE }; flash_write(id, cmd, 1); /* Verify */ while (flash_is_busy(id)); } __STATIC_FORCEINLINE uint8_t flash_at25sl_read_status_register_2(HW_QSPIC_ID id) { __DBG_QSPI_VOLATILE__ uint8_t status; uint8_t cmd[] = { AT25SL_READ_STATUS_REGISTER2 }; flash_transact(id, cmd, 1, &status, 1); return status; } /** * \brief Write the Status Register 2 of the Flash * * \param[in] id QSPI controller id * \param[in] value The value to be written. * * \note This function blocks until the Flash has processed the command. No verification that the * value has been actually written is done though. It is up to the caller to decide whether * such verification is needed or not and execute it on its own. */ __STATIC_FORCEINLINE void flash_at25sl_write_status_register_2(HW_QSPIC_ID id, uint8_t value) { uint8_t cmd[] = { AT25SL_WRITE_STATUS_REGISTER2, value }; flash_write(id, cmd, 2); /* Wait for the Flash to process the command */ while (flash_is_busy(id)); } __STATIC_FORCEINLINE void flash_at25sl_enable_quad_mode(HW_QSPIC_ID id) { uint8_t status; status = flash_at25sl_read_status_register_2(id); if (!(status & AT25SL_STATUS2_QE_MASK)) { flash_write_enable(id); flash_at25sl_write_status_register_2(id, status | AT25SL_STATUS2_QE_MASK); } } __RETAINED_CODE static bool flash_at25sl_is_suspended(HW_QSPIC_ID id) { __DBG_QSPI_VOLATILE__ uint8_t status; status = flash_at25sl_read_status_register_2(id); return (status & AT25SL_STATUS2_SUS_MASK) != 0; } __RETAINED_CODE static void flash_at25sl_initialize(HW_QSPIC_ID id) { flash_at25sl_enable_quad_mode(id); } #endif /* _QSPI_ADESTO_H_ */ /** * \} * \} */

/ ** * \ addtogroup PLA_BSP_SYSTEM * \ {* \ addtogroup PLA_MEMORY * * \ {* / / ** **************************************************************************************** * * @file qspi_at25sl321.h * * @brief QSPI flash driver for the Adesto AT25SL321 * * Copyright (C) 2017-2019 Dialog Semiconductor. * This computer program includes Confidential, Proprietary Information * of Dialog Semiconductor. All Rights Reserved. * **************************************************************************************** */ #ifndef _QSPI_AT25SL321_H_ #define _QSPI_AT25SL321_H_ #ifndef ADESTO_ID #define ADESTO_ID 0x1F #endif // Device type using command 0x9F #define AT25SL321 0x15 #ifndef AT25SL321_32Mb_SIZE #define AT25SL321_32Mb_SIZE 0x16 #endif #include "qspi_common.h" #include "sdk_defs.h" #include "qspi_adesto.h" static void flash_at25sl321_sys_clock_cfg(HW_QSPIC_ID id, sys_clk_t sys_clk); static uint8_t flash_at25sl321_get_dummy_bytes(HW_QSPIC_ID id); static const qspi_flash_config_t flash_at25sl321_config = { .manufacturer_id = ADESTO_ID, .device_type = AT25SL321, .device_density = AT25SL321_32Mb_SIZE, .is_suspended = flash_at25sl_is_suspended, .initialize = flash_at25sl_initialize, .sys_clk_cfg = flash_at25sl321_sys_clock_cfg, .get_dummy_bytes = flash_at25sl321_get_dummy_bytes, .break_seq_size = HW_QSPI_BREAK_SEQ_SIZE_2B, .address_size = HW_QSPI_ADDR_SIZE_24, .page_program_opcode = AT25SL_PAGE_PROGRAM, .page_qpi_program_opcode = AT25SL_PAGE_PROGRAM_QPI, .quad_page_program_address = false, .fast_read_opcode = AT25SL_FAST_READ_QUAD_IO, .erase_opcode = AT25SL_BLOCK_ERASE_4KB, .erase_suspend_opcode = AT25SL_ERASE_PROGRAM_SUSPEND, .erase_resume_opcode = AT25SL_ERASE_PROGRAM_RESUME, .read_erase_progress_opcode = AT25SL_READ_STATUS_REGISTER1, .erase_in_progress_bit = FLASH_STATUS_BUSY_BIT, .erase_in_progress_bit_high_level = true, .send_once = 1, .extra_byte = 0xA0, .ucode_wakeup = {at25sl_ucode_wakeup, sizeof(at25sl_ucode_wakeup)}, .power_down_delay = AT25SL_POWER_DOWN_DELAY_US, .release_power_down_delay = AT25SL_RELEASE_POWER_DOWN_DELAY_US, .power_up_delay = AT25SL_POWER_UP_DELAY_US, .is_ram = false, .qpi_mode = false, .enter_qpi_opcode = AT25SL_ENABLE_QPI, .memory_size = MEMORY_SIZE_32Mb, }; __RETAINED_CODE static void flash_at25sl321_sys_clock_cfg(HW_QSPIC_ID id, sys_clk_t sys_clk) { } __RETAINED_CODE static uint8_t flash_at25sl321_get_dummy_bytes(HW_QSPIC_ID id) { return 1; } #endif /* _QSPI_W32Q32FW_H_ */ /** * \} * \} */

 <配置名称= “MX25U3235F”> 为0x400000   0xa8a500eb   0x00000066   0×01 0×40 0×07   <配置名称= “W25Q32FW”> 为0x400000   0xa82000eb   0x00000066   0X31 0×02 0×07   <配置名称=”GD25LE32 “> 为0x400000   0xa82000eb   0x00000066   0×01 0×00 0×02 0×07   <配置名称=” AT25SL321" >为0x400000   0xa8a000eb   0x00000066   0×01 0×00 0×02 0×07   

<？XML Version =“1.0”编码=“UTF-8”？>   da1469x-00    0x2000   0x2000   AT25SL321  为0x400000   0xa8a500eb   0x66  为0x1为0x0 0X2 0x7的