I have a clean setup, compiled the SPS demo, programmed it in the BASIC kit
Then I hooked it up to a PAN1740. Have set the I2C pins and UART right, connected the JTAG-SWD pins and was able to program the EEPROM with SmartSnippets.
The device advertises and I can connect.
So now I want to overwrite the program with another version so I connect again and it can not find any core connected anymore, changed programmers, tried again. I get this:
[ERROR @15-12-09 23:55:21] No known chip found while opening JLink connection. Terminating proccess...
[INFO @15-12-09 23:55:21] Failed downloading firmware file to the board.
[INFO @15-12-09 23:55:51] Could not measure total IR len. TDO is constant high.
[INFO @15-12-09 23:55:51] Could not measure total IR len. TDO is constant high.
[INFO @15-12-09 23:55:52] Could not measure total IR len. TDO is constant high.
[INFO @15-12-09 23:55:52] Could not measure total IR len. TDO is constant high.
[INFO @15-12-09 23:55:52] Could not measure total IR len. TDO is constant high.
[ERROR @15-12-09 23:55:52] Could not read memory.
[ERROR @15-12-09 23:55:52] No known chip found while opening JLink connection. Terminating proccess...
[INFO @15-12-09 23:55:52] Failed downloading firmware file to the board.
[INFO @15-12-09 23:56:37] Could not measure total IR len. TDO is constant high.
[INFO @15-12-09 23:56:37] Could not measure total IR len. TDO is constant high.
I hooked up the basic board and
[INFO @15-12-09 23:56:37] Found SWD-DP with ID 0x0BB11477
[INFO @15-12-09 23:56:37] FPUnit: 4 code (BP) slots and 0 literal slots
[INFO @15-12-09 23:56:37] Found Cortex-M0 r0p0, Little endian.
[INFO @15-12-09 23:56:38] BTLE device selected.
[INFO @15-12-09 23:56:38] Firmware File C:\ws\SmartSnippets\resources\jtag_programmer.bin has been selected for downloading.
[INFO @15-12-09 23:56:38] Started reading 256 bytes from address 47F00.
[INFO @15-12-09 23:56:38] Reading is complete. Read 256 bytes.
[INFO @15-12-09 23:56:38] Successfully downloaded firmware file to the board.
Connected the PAN1740 again, no changes in setup
[INFO @15-12-09 23:59:50] SYSRESETREQ has confused core. Trying to reconnect and use VECTRESET.
[WARNING @15-12-09 23:59:50] Failed to reset CPU. VECTRESET has confused core.
[WARNING @15-12-09 23:59:50] CPU did not halt after reset.
[WARNING @15-12-09 23:59:50] CPU could not be halted
[INFO @15-12-09 23:59:50] Core did not halt after reset, trying to disable WDT.
[WARNING @15-12-09 23:59:50] CPU did not halt after reset.
[WARNING @15-12-09 23:59:50] CPU could not be halted
[WARNING @15-12-09 23:59:50] Could not set S_RESET_ST
[INFO @15-12-09 23:59:51] SYSRESETREQ has confused core. Trying to reconnect and use VECTRESET.
[WARNING @15-12-09 23:59:51] Failed to reset CPU. VECTRESET has confused core.
[WARNING @15-12-09 23:59:51] CPU did not halt after reset.
[WARNING @15-12-09 23:59:51] CPU could not be halted
[INFO @15-12-09 23:59:51] Core did not halt after reset, trying to disable WDT.
[WARNING @15-12-09 23:59:51] CPU did not halt after reset.
[WARNING @15-12-09 23:59:51] CPU could not be halted
[WARNING @15-12-09 23:59:52] Could not set S_RESET_ST
[ERROR @15-12-09 23:59:52] Failed writing value A7 at address 50000012.
[INFO @15-12-09 23:59:52] Failed downloading firmware file to the board.
So now I'm confused. Any pointers???
Regards, Roland
Hi roland,
你能plase check the selections you have on the Options for Target -> Debug-> Settings and make sure that SW interface is selected (are you able to see your SW device in the dialog box and your Jlink ?), also please have a look at the utilities tab and make sure that the option "Use External Tool for Flash programming is selected".
Thanks MT_dialog
Dear MT_dialog,,
First of all thanks for the quick reply.
I use the SWDIO/SWCLK interface. None of the settings other than changing between seggers and tried again.
One thing I experienced is the following output in SmartSnippets when I started again:
[INFO @15-12-10 22:22:14] TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
[INFO @15-12-10 22:22:16] ID mismatch. Expected 0223, found 2A74
…另一个7试…
[INFO @15-12-10 22:22:19] ID mismatch. Expected 0223, found 2A74
[ERROR @15-12-10 22:22:19] Could not read memory.
[ERROR @15-12-10 22:22:19] No known chip found while opening JLink connection. Terminating proccess...
[INFO @15-12-10 22:22:19] Ongoing debug mode already disabled.
[INFO @15-12-10 22:22:19] Failed downloading firmware file to the board.
I prepared a fresh and new PAN1740 equipped PCB and bingo it works directly. I can connect, read OTP, EEPROM as what was possible before with the "defective" PAN1740.
I prepared another fresh and third PAN1740 based board and programmed it. With this one I can do everything as expected.
So I have now 2 out of 3. But no real explanation. I traced back what I have done...
1)could I have changed a setting in SmartSnippets?
-- nothing that could damage the processor/OTP as the Vpp is not connected.
2) could I have done something in the code that could lock up the device?
-- the settings in the da14580_config.h file have changed, however the change seems unrelated.
/*Build for OTP or JTAG*/
#define DEVELOPMENT_DEBUG 0 //0: code at OTP, 1: code via JTAG
-----> Putting code in EEPROM is the same as if it were the OTP for the compiler I presume, so this should be "0"
/*Application boot from OTP memory - Bootloader copies OTP Header to sysRAM */
#undef APP_BOOT_FROM_OTP
-----> This must be #undef when using an EEPROM instead of the OTP itself?
/*NVDS structure is padded with 0 - NVDS struture data must be written in OTP in production procedure*/
#undef READ_NVDS_STRUCT_FROM_OTP
----> with the defective PAN the READ_NVDS_STRUCT_FROM_OTP was set as #define. WIth the two other PAN's it was set to #undef. Reason to change was the tip I got to check this because the defined name in .NVDS_TAG_DEVICE_NAME would not appear.
So what would be an educated guess on why the PAN1740 cannot be connected to anymore?
Best regards,
R
Hi ronald,
There nothing you can do to your software so that keil or smart snippets not to be able to connect with it. Also in smart snippets since you are using the JTAG interface there is no configuration you can tweak in order to break communication to the da. Since you are in development mode you should leave the CFG_DEVELOPMENT_DEBUG to 1 since it will help you to trace errors and make your life easier, but still this isn't the reason your device cant connect. Have you tried to download code to the PAN by using the UART interface ? Also are you able to see your device through keil, read its S/N for example ?
Thanks MT_dialog