GreenPAK Diagram

Design Steps

1. Configure four GPIO pins as digital input/outputs with the output mode set to open drain NMOS.
2. Configure one pin as a digital input for the enable signal.
3. Add an AND gate to each input/output.
4. Configure four multi-function blocks (or four LUTs and four CNT/DLY blocks if Multi-function blocks aren’t available) as a NOR gate feeding into a falling edge delay.
5. Select OSC2 as the clock source for the delay blocks and set it to“Force Power On.”

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